FPGA on KAD https://www.kad8.com/tags/fpga/ Recent content in FPGA on KAD Hugo -- gohugo.io en © 2026 Sat, 04 Jul 2026 10:56:32 +0800 AMD Versal Premium Gen 2 MoP: 32GB LPDDR5X, Memory-on-Package, and a 15-Year Lifecycle https://www.kad8.com/hardware/amd-versal-premium-gen-2-mop-32gb-lpddr5x-memory-on-package-and-a-15-year-lifecycle/ Sat, 04 Jul 2026 10:56:32 +0800 https://www.kad8.com/hardware/amd-versal-premium-gen-2-mop-32gb-lpddr5x-memory-on-package-and-a-15-year-lifecycle/ Lattice Acquires AMI for $1.65B to Expand AI and Cloud Strategy https://www.kad8.com/news/lattice-acquires-ami-for-1.65b-to-expand-ai-and-cloud-strategy/ Tue, 05 May 2026 10:05:24 +0800 https://www.kad8.com/news/lattice-acquires-ami-for-1.65b-to-expand-ai-and-cloud-strategy/ 6 ns Hardware Timer: IEEE TC Breakthrough for RDMA and DPU https://www.kad8.com/network/6-ns-hardware-timer-ieee-tc-breakthrough-for-rdma-and-dpu/ Thu, 30 Apr 2026 16:47:53 +0800 https://www.kad8.com/network/6-ns-hardware-timer-ieee-tc-breakthrough-for-rdma-and-dpu/ Altera in 2026: Intel, Silver Lake, and the FPGA Reset https://www.kad8.com/hardware/altera-in-2026-intel-silver-lake-and-the-fpga-reset/ Mon, 20 Apr 2026 23:20:14 +0800 https://www.kad8.com/hardware/altera-in-2026-intel-silver-lake-and-the-fpga-reset/ Altera’s Spin-Off: Intel’s Strategic Reset and the FPGA Market Shift https://www.kad8.com/hardware/alteras-spin-off-intels-strategic-reset-and-the-fpga-market-shift/ Thu, 16 Apr 2026 18:02:04 +0800 https://www.kad8.com/hardware/alteras-spin-off-intels-strategic-reset-and-the-fpga-market-shift/ Revisiting PCI–RapidIO Bridge Driver Design on VxWorks: A 2026 Perspective https://www.kad8.com/bsp/revisiting-pcirapidio-bridge-driver-design-on-vxworks-a-2026-perspective/ Sun, 08 Mar 2026 18:00:00 +0800 https://www.kad8.com/bsp/revisiting-pcirapidio-bridge-driver-design-on-vxworks-a-2026-perspective/ DDR Memory Technology Explained: From DDR to DDR5 https://www.kad8.com/hardware/ddr-memory-technology-explained-from-ddr-to-ddr5/ Sun, 25 Jan 2026 20:27:47 +0800 https://www.kad8.com/hardware/ddr-memory-technology-explained-from-ddr-to-ddr5/ DDR Memory Fundamentals: Architecture, Prefetch, and Addressing https://www.kad8.com/hardware/ddr-memory-fundamentals-architecture-prefetch-and-addressing/ Sat, 24 Jan 2026 18:42:35 +0800 https://www.kad8.com/hardware/ddr-memory-fundamentals-architecture-prefetch-and-addressing/ Getting Started with FPGA: From Glue Logic to Reconfigurable Superchips https://www.kad8.com/hardware/getting-started-with-fpga-from-glue-logic-to-reconfigurable-superchips/ Thu, 07 Aug 2025 00:07:01 +0800 https://www.kad8.com/hardware/getting-started-with-fpga-from-glue-logic-to-reconfigurable-superchips/ 40 Years of FPGA: From Xilinx Logic to Edge AI https://www.kad8.com/ai/40-years-of-fpga-from-logic-cleanup-to-ai-acceleration/ Mon, 04 Aug 2025 20:57:34 +0800 https://www.kad8.com/ai/40-years-of-fpga-from-logic-cleanup-to-ai-acceleration/ Designing and Configuring VxWorks 7 for Zynq 7000 https://www.kad8.com/bsp/designing-and-configuring-vxworks-7-for-zynq-7000/ Sun, 23 Mar 2025 10:50:11 +0800 https://www.kad8.com/bsp/designing-and-configuring-vxworks-7-for-zynq-7000/ Boot VxWorks With Altera Cyclone V https://www.kad8.com/bsp/booting-vxworks-with-altera-cyclone-v/ Mon, 07 Oct 2024 15:04:11 +0800 https://www.kad8.com/bsp/booting-vxworks-with-altera-cyclone-v/