Intel’s Big-Cache Strategy: 144MB bLLC to Rival AMD 3D V-Cache #
Recent leaks suggest that Intel’s upcoming Nova Lake processors may integrate a massive 144MB of additional Last-Level Cache (bLLC)—a clear move to counter AMD’s successful 3D V-Cache designs. While earlier reports hinted at widespread adoption, new information indicates that the large cache may be initially exclusive to unlocked Core Ultra SKUs.
Industry chatter reinforces the idea that Intel is preparing gaming-focused desktop and mobile processors to go head-to-head with AMD’s Ryzen X3D lineup once Nova Lake arrives.
Which Nova Lake Models Might Include bLLC? #
Leaks indicate that Nova Lake chips using an 8 P-core + 16 E-core configuration are the most likely to receive the expanded cache. These variants would fit into the Core Ultra 5 or higher product tiers.
Importantly, no reliable evidence suggests that overclockable SKUs will exclude bLLC—many details remain unconfirmed.
Leaked Nova Lake Core Configurations #
- Core Ultra 9:
Up to 16 P-cores + 32 E-cores + 4 LP-E cores; ~150W TDP - Core Ultra 7:
14 P-cores + 24 E-cores + 4 LP-E cores; ~150W - Core Ultra 5 variants:
- 8P + 16E + 4 LP-E (125W, rumored bLLC)
- 8P + 12E + 4 LP-E (125W, rumored bLLC)
- 6P + 8E + 4 LP-E (125W, no large cache)
- Core Ultra 3:
- 4P + 8E + 4 LP-E (65W)
- 4P + 4E + 4 LP-E (65W)
These lineups align with earlier leaks describing 52-core, 28-core, and 16-core compute tile designs, though final production plans remain uncertain.
What the 144MB Cache Actually Represents #
The rumored 144MB does not include per-core L2 or L3 cache.
Instead, it is an additional stacked cache layer placed on the compute tile to act as an extended last-level cache.
Some insiders claim that high-end Core Ultra 9 models may feature a dual bLLC tile layout, increasing total LLC capacity to around 180MB—potentially surpassing AMD’s current 3D V-Cache models in raw cache size.
New Leak: bLLC Positioned Inside the Compute Tile #
Early speculation suggested a system-level cache located on an I/O or base tile.
But the latest information points to a different design:
- bLLC sits directly in the compute tile,
- works as the tile’s exclusive last-level cache,
- and behaves similarly to a traditional L3/L4 expansion.
This closer placement should help reduce latency and improve bandwidth for workloads that depend heavily on cache efficiency—especially games and HPC applications.
Intel vs. AMD: A Renewed Cache Arms Race #
Intel’s bLLC appears to be their primary countermeasure to AMD’s maturing 3D V-Cache technology. AMD’s Ryzen 9000X3D processors have shown:
- substantial gaming performance improvements,
- better overclocking flexibility than early X3D chips,
- and strong gains in cache-bound workloads.
Intel seems poised to apply bLLC first to unlocked SKUs, allowing enthusiasts to benefit from both expanded cache and frequency scaling. Depending on reception, Intel may later extend bLLC to locked models.
Roadmap Outlook: Nova Lake vs. Zen 6 #
AMD plans continued advancement of 3D V-Cache in the Zen 6 era, including refinements to stacking and gaming performance. Intel, meanwhile, aims to deliver:
- larger core counts,
- faster memory support,
- improved I/O layouts,
- and new cache-enhanced compute tiles.
If Intel succeeds in mass-producing bLLC-equipped Nova Lake chips, the next generation may ignite the fiercest competition yet in the large-cache CPU market—reshaping expectations for gaming and high-performance computing.