At the 2024 IEEE International Electron Devices Meeting (IEDM), Intel presented one of its most forward-looking technology disclosures in years. Rather than incremental node updates, the focus was on fundamental materials, interconnect physics, and packaging scalability—all aimed at extending Moore’s Law toward a long-term goal of one trillion transistors in a single package by 2030.
These announcements came from Intel’s Foundry Technology Research organization and outline how logic, wiring, and assembly must evolve together to sustain progress beyond the limits of silicon scaling.
🧬 2D Transistor Breakthroughs: Life After Silicon #
As conventional silicon channels struggle at atomic dimensions, Intel is aggressively investing in 2D transition metal dichalcogenide (TMD) materials. These materials are only a few atoms thick, enabling electrostatic control that silicon can no longer provide at extreme scales.
Key highlights include:
- 300mm Wafer Integration: Intel demonstrated the industry’s first wafer-scale integration of both NMOS and PMOS 2D transistors on standard 300mm wafers—an essential requirement for manufacturability.
- Molybdenum-Based FETs: Using molybdenum-based TMDs, Intel achieved 30nm gate lengths with drive currents that exceed previous academic results, signaling real device viability rather than lab curiosities.
- Ultra-Low Voltage Operation: These devices are being designed to operate at sub-300mV, a critical threshold for reducing leakage, heat density, and overall energy consumption in future AI accelerators.
Rather than replacing RibbonFET in the near term, Intel positions 2D materials as a post-silicon channel option that can slot into future gate-all-around and stacked transistor concepts.
🔗 Interconnect Innovation: Subtractive Ruthenium Takes Over #
At advanced nodes, transistors are no longer the dominant limiter—wires are. Copper interconnects suffer from rising resistance and parasitic capacitance as dimensions shrink below 20nm.
Intel’s answer is Subtractive Ruthenium (Ru) interconnect technology:
- Lower Capacitance: By combining ruthenium wiring with engineered air gaps, Intel demonstrated up to a 25% reduction in line-to-line capacitance.
- Tighter Pitch: This enables interconnect scaling down to 18nm pitch, supporting higher transistor densities without crippling signal delay.
- Manufacturing Simplicity: Subtractive Ru avoids some of the complex barrier and liner requirements of copper, potentially simplifying future back-end-of-line processes.
As logic density increases, these wiring improvements are just as critical as transistor scaling itself.
📦 Packaging Revolution: SLT and EMIB-T #
Intel made it clear that advanced packaging is now the primary scaling vector for high-performance systems.
Selective Layer Transfer (SLT) #
- 100× Throughput Gain: SLT uses an inorganic infrared laser debonding process to rapidly and precisely transfer thin chiplet layers.
- Assembly Bottleneck Solved: Compared to traditional pick-and-place methods, SLT increases chiplet assembly throughput by two orders of magnitude, addressing one of the biggest constraints in large multi-die systems.
EMIB-T: A New Class of Bridge #
- TSV-Enabled EMIB: EMIB-T is the first Embedded Multi-die Interconnect Bridge to incorporate Through-Silicon Vias directly in the bridge.
- Logic-to-HBM Optimization: This dramatically improves power delivery and signal integrity between compute chiplets and stacked HBM, a critical requirement for future AI systems.
Together, SLT and EMIB-T position Intel to scale not just performance—but manufacturability—of massive chiplet assemblies.
🧭 The Road to 2030: A Full-Stack Strategy #
Intel framed these advances as part of a tightly integrated roadmap rather than isolated research projects.
- Five Nodes in Four Years: RibbonFET, PowerVia, and advanced interconnects remain the near-term foundation.
- Trillion-Transistor Vision: By 2030, Intel expects packages containing up to one trillion transistors, enabled by massive chiplet counts rather than monolithic dies.
- Extreme Package Scale: Future system-in-package designs are targeting sizes up to 120 × 180 mm—roughly 12× larger than today’s flagship AI processors—housing dozens of compute tiles and HBM stacks interconnected via EMIB-T.
🧠 Final Perspective #
Intel’s IEDM 2024 disclosures underscore a critical reality of modern semiconductor scaling: no single breakthrough is sufficient. Transistors, wires, and packaging must advance together—or progress stalls.
By investing simultaneously in 2D materials, next-generation interconnects, and high-throughput packaging, Intel is betting that Moore’s Law doesn’t end—it simply changes form. Whether this vision reaches full production by 2030 remains to be seen, but the technical foundation is now firmly in place.