NVIDIA Rosa CPU Targets TSMC A16 for Next-Generation AI Performance
As AI workloads become increasingly dependent on complex orchestration, autonomous agents, and large-scale inference pipelines, CPU performance is once again taking center stage. While GPUs continue to dominate parallel computation, many AI frameworks still rely heavily on strong single-threaded CPU execution for scheduling, tool invocation, runtime management, and serial code execution.
According to recent supply chain reports, NVIDIA’s next-generation Rosa CPU architecture is being designed with exactly this challenge in mind. Built around an entirely new Rigel Arm-based core architecture, Rosa is expected to utilize TSMC’s advanced A16 (1.6nm) or next-generation 2nm-class manufacturing technologies to deliver significantly higher per-core performance for future AI infrastructure.
The Rosa platform is reportedly scheduled to debut in data centers alongside NVIDIA’s Feynman GPU around 2029, with consumer-oriented products expected to follow in the next generation of AI PCs.
🚀 TSMC A16 Becomes the Preferred Manufacturing Node #
NVIDIA is expected to manufacture the Rosa CPU family using TSMC’s most advanced fabrication technologies.
While the standard N2P process remains a possible option, industry reports indicate that NVIDIA is prioritizing the more advanced A16 node.
The primary reason is a key architectural feature unique to A16: Super Power Rail (SPR).
Backside Power Delivery Changes Chip Design #
Super Power Rail introduces Backside Power Delivery (BPD), a manufacturing innovation that physically separates signal routing from power distribution.
In conventional semiconductor designs:
- Signal routing.
- Clock distribution.
- Power delivery.
all occupy the front side of the silicon wafer, increasing routing congestion and electrical interference.
Backside Power Delivery relocates the power network to the reverse side of the wafer while reserving the front side exclusively for signal routing.
This cleaner physical layout improves electrical efficiency and enables higher operating performance within the same chip footprint.
Expected A16 Advantages #
Compared with conventional N2P manufacturing, TSMC’s A16 process is expected to provide:
- 8–10% higher performance at equivalent voltage.
- 15–20% lower power consumption at the same performance level.
- Approximately 10% higher transistor density.
For high-performance AI processors, these improvements translate into more compute resources while maintaining manageable thermal and power characteristics.
🏭 Manufacturing Complexity Increases Across the Supply Chain #
Although Backside Power Delivery offers significant performance benefits, it also introduces new manufacturing challenges.
The additional process steps required by A16 will increase demand for specialized semiconductor manufacturing equipment and materials.
Higher Demand for CMP Processing #
Backside Power Delivery requires extremely precise polishing of the wafer after backside processing.
This significantly expands the use of Chemical Mechanical Polishing (CMP) throughout production.
Industry estimates suggest:
- Standard 2nm manufacturing already requires roughly twice as many CMP steps as 7nm production.
- Adding Backside Power Delivery increases CMP consumable demand by an additional 15–20%.
As advanced nodes scale toward mass production, CMP equipment suppliers and material vendors are expected to benefit from higher manufacturing volumes.
Carrier Wafer Consumption Also Rises #
Advanced backside processing also increases the use of carrier wafers, temporary support substrates used during wafer thinning and polishing.
Compared with reclaimed wafers, carrier wafers command significantly higher average selling prices, making them an attractive growth opportunity for specialized semiconductor suppliers.
As adoption of A16 expands, demand for these high-value manufacturing materials is expected to grow alongside advanced AI processor production.
⚙️ Rigel: NVIDIA’s Next Custom Arm CPU Core #
The Rosa platform introduces NVIDIA’s next-generation custom CPU architecture, codenamed Rigel.
Unlike traditional server processors that emphasize maximum core counts, Rigel reportedly prioritizes single-threaded execution performance, addressing an increasingly important bottleneck in modern AI systems.
Why Single-Thread Performance Matters for AI #
Many AI applications remain partially sequential despite massive GPU acceleration.
Examples include:
- AI agent orchestration.
- Python runtime execution.
- Tool invocation pipelines.
- Sandbox evaluation.
- Workflow scheduling.
- Operating system coordination.
Improving single-thread latency can therefore accelerate overall AI application responsiveness, even when most computation occurs on GPUs.
📊 NVIDIA’s CPU Roadmap Continues to Evolve #
Rosa represents the third major step in NVIDIA’s modern Arm CPU strategy.
| Feature | Grace (2023) | Vera (2026) | Rosa (Expected 2028–2029) |
|---|---|---|---|
| CPU Architecture | Arm Neoverse V2 | Custom Olympus | Custom Rigel |
| Instruction Set | Arm | Arm v9.2 | Arm v9.2 |
| Core Configuration | 72C / 72T | 88C / 176T | Expected 128+ cores |
| Primary Focus | HPC | AI Factory Performance | Agentic AI & AI orchestration |
| L2 Cache | 1MB per core | 2MB per core | Larger than Vera |
| Memory | LPDDR5X | LPDDR5X + SOCAMM | LPDDR6 / LPDDR6X |
Compared with Grace and Vera, Rosa is expected to place even greater emphasis on per-core execution efficiency rather than simply increasing overall core counts.
🧠 Architecture Designed for Future AI Workloads #
Reports suggest Rigel achieves higher performance through architectural improvements instead of substantially increasing silicon area.
Expected enhancements include:
- Improved instruction delivery.
- Larger cache hierarchy.
- More efficient memory access.
- Better execution pipeline utilization.
This design philosophy allows NVIDIA to improve performance while maintaining similar physical package dimensions, simplifying deployment in existing server platforms.
Although complete specifications have not yet been disclosed, future Rosa processors are expected to include:
- Larger cache configurations.
- Faster proprietary interconnects.
- LPDDR6 or LPDDR6X memory.
- Higher memory bandwidth than previous generations.
Together, these improvements aim to eliminate CPU bottlenecks in increasingly complex AI software stacks.
💾 Memory Architecture Evolves Alongside Compute Performance #
Memory bandwidth is becoming just as important as raw CPU throughput.
Previous NVIDIA CPU generations have steadily expanded memory capabilities:
- Grace introduced LPDDR5X with bandwidth up to 512 GB/s.
- Vera expanded support through LPDDR5X and SOCAMM, reaching approximately 1.2 TB/s.
- Rosa is expected to transition to LPDDR6 or LPDDR6X, further increasing available memory bandwidth.
As AI models continue growing in size and complexity, faster memory subsystems will become essential for feeding data to both CPUs and GPUs efficiently.
🏁 Rosa Signals NVIDIA’s Long-Term AI Infrastructure Strategy #
Although Rosa remains several years from commercial availability, the platform illustrates NVIDIA’s broader strategy of optimizing every layer of AI infrastructure.
By combining:
- Custom Arm-based Rigel CPU cores.
- TSMC’s advanced A16 manufacturing technology.
- Backside Power Delivery.
- Higher transistor density.
- Next-generation LPDDR6 memory.
- Continued CPU-GPU co-design.
NVIDIA is positioning Rosa as a key component of future AI data centers built for increasingly autonomous, agent-driven workloads.
While final specifications—including core counts, clock frequencies, interconnect bandwidth, and power envelopes—remain unconfirmed, Rosa is shaping up to be a significant evolution in NVIDIA’s custom CPU roadmap, with a clear emphasis on maximizing single-threaded performance for next-generation AI computing.